Posted On May 03

Senior FPGA Design Engineer


Location : Bengaluru, Karnataka

Headquarters : United States

Hiring Mode : Full Time

Experience : Senior Level

Job Description
Job Description

As a Senior FPGA Design Engineer within the Design Creation and Debug Group, you can expect to work on the RTL underpinnings Intel PSG's System-on-Chip integration tool, Platform Designer, FPGA Debug Environment Tools such as SignalTap and System Console and next generation FPGA-based soft processors and uControllers. The goal of this team is to implement powerful embedded hardware systems a straightforward and enjoyable task from design creation through debugging and performance optimization. The team is responsible for development of RTL for various IPs, including the on-chip Memory Mapped Interconnect ( AXI/APB/AHB/Avalon) , streaming protocols IPs ( AXI / Avalon ), debug IP such as signaltap, ISSP, ISMCE, bridge and adapter IP, various soft processor implementations and supporting a full stack of tools which assemble these IPs in interesting and dynamic ways.

As a Hardware Engineer in this position, you will need to be an excellent at digital design with expertise in Verilog/System Verilog. Some larger projects we're undertaking include:

� Coming up with newer versions of on-chip transfer protocols aimed for high speed on hyperflex and eASIC architectures
� Developing new interconnect topologies to maximize data transfer throughput over long distances over FPGAs
� Extending support for AXI and other Industry Standard Memory Mapped and Streaming protocols
� Developing robust IP and networks which customers use in mission critical debug environments
� Developing microprocessor and microcontroller architectures optimized for implementation on Intel FPGAs

We've assembled an energetic team of quality people and are looking for a couple more experienced engineers to help with the effort.

The HDL engineer will have a direct influence on our customers and the adoption of our products, with tasks including the following:
� Work closely with developers across software, RTL IP and embedded engineering to ensure we develop design flows that meet our customers' needs
� Guide IP release content, and serve as a liaison with the support, field, marketing, and product planning organizations
� Research, define, and validate key customer use cases
� Create reference RTL designs
� Use Intel FPGA design tools like our customers to identify usability and productivity problems or missing features


� BS/MS/PhD degree in Electrical/Computer/Software Engineering or equivalent and 8+ years of relevant industry experience
� Strong understanding and knowledge of digital design/Timing Closure concepts/Fundamentals of Verification/Hardware Debug
� Strong experience Verilog and System Verilog
� Understanding of RiscV and MIPS processor design
� Understanding of Computer Architecture/ARM Based Bus Protocols
� Understanding of other communication protocols will be plus
� Knowledge of Quartus tool flow
� Tcl, Perl, and/or Python scripting skills
� Dedication to customer experience and usability
� Strong written and oral communication skills
� Ability to influence across organization boundaries

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

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