Server SoC Post-Si System Validation Engineer
Location : Bengaluru, Karnataka
Headquarters : United States
Hiring Mode : Full Time
Experience : Mid Level
Usage of any Post-Si debug tools e.g., logic analyzers, oscilloscopes, things like Chip Scope on FPGA's C C++ and Python are the most useful languages for our work. VLSI concepts Power Management resent Familiarity with FW (embedded uC debug ARC or Extensa LX series uC preferred Knowledge of ARM PM concepts e.g PQ channel General clocking concepts PLL's, RO's, etc Ability to debug interactions between different microcontrollers Understanding power delivery concepts, VR interactions, etc Mesh Coherency Knowledge of coherence algorithm MESI, MOESI, MESIF, etc Experience with SoC fabrics (AXI, ACE or other AMBA protocols Understanding transaction flows through the system. PCI Express we can leverage this expertise for other IO's, like CXL Familiarity with any generation of the PCI Express specification Usage of 3rd party PCIe Analyzers very helpful Tek, Lecroy Memory Expertise in any DDR technology. Usage of 3rd party DDR Analyzers very helpful Tek, Lecroy, etc Other useful backgrounds Security, Virtualization, RAS
The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.
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